High Resolution DPW Modulator based on FPGA with Linear behavior of system

  • Mayur S Patil University of Pune
  • Ashish B Vartak
Keywords: Field Programmable gate arrays (FPGA), Power conversaation, Power converters PWM

Abstract

Digital pulse width modulator (DPWM) have so many advantages in Power Electronics field. So there is increase in use of DPWM in various applications. There are so many DPWM designing techniques are available. Among these, the classical design techniques will require higher frequency clock signals. Also the linearity in the output is lost. This paper presents a design to increase the resolution of the DPWM with more linearity in the output which can be simulated and tested on field programmable gate arrays (FPGA). In some designs implemented FPGA have large code length. The proposed method is based on the on-chip digital clock manager block (DCM) present in the low-cost Spartan-3 FPGA series which helps to introduce new method of generating DPWM. Implementation of this will be very helpful considering various industrial applications.

References

[1] Rahim N.A. and Islam Z., “Field Programmable Gate ArrayBased Pulse- Width Modulation for Single Phase Active Power Filter”; American Journal of Applied Sciences, Vol.6 (2009): pp. 1742- 1747. [2] A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, “Digital pulse width modulator architectures,” in Proc. IEEE 35th Annu. Power Electron. Spec. Conf., Jun. 2004, vol. 6, pp. 4689–4695. [3] J. Li, Y. Qiu, Y. Sun, B. Huang, M. Xu, et al, “High Resolution Digital Duty Cycle Modulation Schemes for Voltage Regulators,” in Proc. IEEE 22nd Applied Power Electronics Conf. (APEC‟07), 2007, pp. 871–876. [4] B. Cougo, T. Meynard, and G. Gateau, “Parallel three-phase inverters: Optimal PWM method for flux reduction in Intercell transformers,” IEEE Trans. Power Electron., vol. 26, no. 8, pp. 2184–2191, 2011. [5] S. C. Huerta, A. de Castro, O. Garcia, and J. A. Cobos, “FPGA-based digital pulse-width modulator with time resolution under 2 ns,” IEEE Trans. Power Electron., vol. 23, no. 6, pp. 3135–3141, Nov. 2008. [6] A. deCastro and E. Todorovich, “DPWM based on FPGA clock phase shifting with time resolution under 100 ps,” in Proc. IEEE Power Electron. Spec. Conf., 2008, pp. 3054–3059. [7] D. Navarro, L. A. Barrag´an, J. I. Artigas, I. Urriza, O. Luc´ıa, and O. Jim´enez, “FPGA-based high-resolution synchronous digital pulse width modulator,” IEEE Int. Symp. Ind. Electron., pp. 2771–2776, 2010. [8] Spartan-3 FPGA family Data sheet. [9] Spartan-3 Generation FPGA User Guide, UG331 (v 1.5), Xilinx, San Jose, CA, 2009, ch.3. [10] A. de Castro and E. Todorovich, “DPWM based on FPGA clock phase shifting with time resolution under 100 ps,” in Proc. IEEE Power Electron. Spec. Conf., 2008, pp. 3054–3059. [11] R. Andrew and S. Poriazis, “Design of synchronous circuits with multiple clocks,” in Proc. IEEE Int. Symp. Circuits Syst., 1995, vol. 2, pp. 933–936.
Published
2018-03-21
How to Cite
Patil, M., & Vartak, A. (2018). High Resolution DPW Modulator based on FPGA with Linear behavior of system. Asian Journal For Convergence In Technology (AJCT) ISSN -2350-1146, 2(2). Retrieved from http://www.asianssr.org/index.php/ajct/article/view/184
Issue
Vol 2 (2016): Issue III
Section
Article

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