Partially Adaptive Cluster Based Routing for Network-on-Chip
Abstract
As the technology is scaling, reducing wire delays is the major hurdle in increasing communication speed between the cores of System-on-Chip (SoC). Also in today’s technology 50% of silicon area is occupied by interconnects. Efficient use of interconnects is possible due to highly scalable and reliable Network-on-Chip (NoC) communication architecture which has replaced long buses by routers. Routers in NoC make use of intelligent routing algorithms to route the information reliably between the cores irrespective of the topology used. With the help of routing algorithms router optimizes the use of interconnects. Algorithms should provide deadlock free and congestion free routing while ensuring the reachability to destination. This paper presents partially adaptive Cluster based routing referred to as Cluster based routing for regular mesh topology which, (i) Uses cluster approach to reduce the size of routing table. For a 8x8 Mesh there is 76.57% area reduction in routing table. (ii) Provides deadlock free partially adaptive algorithm without use of virtual channels which is achieved by avoiding cyclic paths. (iii) Uses adaptivity to avoid congestion by uniform distribution of traffic between cores.
References
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