VLSI ARCHITECTURES FOR 2-D DISCRETE WAVELET TRANSFORM USING KS ADDER
Abstract
Discrete wavelet transform (DWT) is a mathematical technique that provides a new method for signal processing. It decomposes a signal in the time domain by using dilated / contracted and translated versions of a single basis function. The 2-D DWT is highly computation intensive and many of its application need real-time processing to deliver better performance. The 2D DWT is currently implemented in very large scale integration (VLSI) system to meet the space-time requirement of various real-time applications. Several design schemes have been suggested for efficient implementation of 2-D DWT in a VLSI system. The proposed 2-D DWT is implementation in Vedic multiplier with kogge stone adder. This design is efficient area and minimized delay in existing design.
References
[9] Mohanty, B.K., and Mahajan, A. (2013b), ―Schedulingscheme and parallel structure for multilevel lifting 2-D DWT without using frame-buffer,‖ IET Circuits, Devices and Systems, doi: 10.1049/iet-cds.2012.0398. [10] Ms. G. R. Gokhale and Ms. P. D. Bahirgonde, ―Design of Vedic-Multiplier using Area-Efficient Carry Select Adder‖, 978-1-4799-8792-4/15/$31.00 c 2015 IEEE. [11] Ms. G. R. Gokhale and Mr. S. R. Gokhale, ―Design of Area and Delay Efficient Vedic Multiplier Using Carry Select Adder‖, 978-1-4673-7758-4/15/$31.00 ©2015 IEEE.
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