Analysis and Comparison of Methods to Reduce Leakage Power and Latency to Improve Performance of VLSI Circuits
Abstract
Power dissipation in one of the major concerns of VLSI circuit designers with the launch of battery held devices and applications, power consumption in the circuit also increased exponentially. Leakage current became an overriding factor in nanometer CMOS design technologies. This paper provides a comprehensive study, analysis and comparison of leakage power reduction technique such as zigzag approach, multi threshold approach, sleepy stack, dual sleep, transistor gating etc.. All the above methods are tested and analyzed using microwind EDA tool.
References
0 International Journal of Advance Research in Science and Engineering Volume No2 Issue 12, December 2013 [9] K. Gnana Deepika, K. Mariya Priyadarshini and K. David Solomon Raj “Sleepy Keeper Approach for Power Performance Tuning in VLSI Desig” International Journal of Electronics and Communication Engineering. ISSN 0974-2166 Volume 6, Number 1 (2013), pp. 17-28 [10]Se Hum Kim Vincent J Mooney3 Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design [11]Chu, R.C., Simons, R.E., and Chrysler, G.M., “Experimental Investigation of an Enhanced Thermo syphon Heat Loop for Cooling of a High Performance Electronics Module,” Proceedings of the 15th IEEE Semiconductor Thermal Measurement and Management Symposium [12] S.Samanta“ Power Efficient VLSI Inverter Design using Adiabatic Logic and Estimation of Power dissipation using VLSIEDA Tool” Special issue of International Journal of computer communication Technology.vol 2.isuue 2,3,4.pp300-303. 2010.
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